1. Field of the Invention
The present invention relates to a layout of an integrated circuit, and more particularly to a layout of a power device.
2. Description of Related Art
The power device (for example, a power amplifier) of an integrated circuit needs to have several groups of circuit units connected and output in parallel in order to satisfy the large power requirements of the next circuit stage. In some particular applications (for example, high frequency operations), the internal layout of the power device often directly affects the performance. For example, the non-symmetric connective relationships between transistors in the layout will often lead to mismatches. When micro-mismatch between the parallel-connected transistors of the power amplifier, one of the transistors may operate at a temperature environment higher than the other transistors. Since the operating current of a transistor is closely related to the temperature gradient, the foregoing transistor often operates with a larger operating current (or smaller operating current) than the others. Because the current output from the power amplifier is quite large, the current is often large enough to damage the mismatched transistor so that the remaining transistors must take up the total output current.
For complementary metal oxide semiconductor (CMOS) device, a rise in temperature will lead to a lowering of the current. Because the power amplifier drives a heavy load, a portion of the remaining transistors may malfunction due to the overheating resulting from the rise in temperature. When more and more transistors fail, the remaining transistors have to take up a heavier load. Thus, the more current flowing through the transistors, the higher will be the temperature. Ultimately, a chain reaction may occur to shut down the entire power amplifier.
In U.S. Pat. No. 6,448,858, the commonly used H-tree structure for the clock tree synthesizing of digital circuit is used to resolve the problem. This conventional technology provides a single-ended solution for a parallel-connected power amplifier. For radio frequency amplifiers, a larger power output is required to drive the next circuit stage. Therefore, a number of amplifying circuit units connected in parallel is required in the amplifier to provide a sufficiently large power output. To prevent different signal phases in each amplifying circuit unit, the conventional technique uses a symmetrical H-shaped layout design to transmit an input signal to each amplifying circuit unit. Through the H-shaped layout, approximately equal length between the signal input end and the amplifying circuit units are ensured and differences between the phases of input signals to the amplifying circuit units are avoided. Through the H-shaped layout, current can be evenly distributed to each transistor to avoid the mismatch problem. Although the conventional technique is able to confer geometric symmetry to the input signal paths, the same does not apply to the output signal paths. In other words, the layout cannot balance the input signal path and the output signal path at the same time. If the connectivity from each transistor to the next stage is too complicated, significant signal loss may result. For high frequency power amplifier, it is advantageous to have both the input signal path and the output signal path symmetrically balanced.
The foregoing technique is only applicable to single-ended circuits. In recent years, most analog or radio frequency signals use a differential circuit because it has better noise rejection. The foregoing H-shaped layout has difficulties applying to a differential circuit. If the H-shaped layout is applied to a differential pair, cross talk between metal interconnects is a problem.